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Transpilation and basis gates
What the compiler does in four stages, what the optimisation levels change, and how to read the Compile preview.
- List the four transpiler stages.
- Rewrite an H gate in the {rz, sx, x} basis.
- Choose an optimisation level and justify it.
- Init: unroll custom gates to the standard library.
- Layout: assign each virtual qubit to a physical one, preferring well-connected, low-error qubits.
- Routing: insert SWAPs so every two-qubit gate acts on neighbours.
- Translation and optimisation: rewrite in the basis gates and cancel what cancels.
Watch H become three gates
Press Compile for a fake backend: the preview lists depth and ops before and after, and 'View circuit' shows rz, sx, rz on each qubit plus the native two-qubit gate. Click 'Edit this circuit' to work with the compiled form.
OPENQASM 3.0; include "stdgates.inc"; qubit[2] q; bit[2] c; h q[0]; cx q[0], q[1]; c = measure q;
| Level | What it does | Use when |
|---|---|---|
| 0 | layout + routing + translation only | you want to see the raw mapping |
| 1 | light optimisation, cancels adjacent inverses | default for quick runs |
| 2 | commutation analysis, better layout search | most hardware jobs |
| 3 | heavy resynthesis of two-qubit blocks | final submission, slower compile |
Why are rz gates essentially free on IBM hardware?
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Compare levels shows level 3 with fewer two-qubit gates than level 1. What is the cost?
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The transpiler lays out, routes, translates and optimises. Read the before/after numbers, prefer level 2 or 3 for hardware, and remember that rz is free while every SWAP is three two-qubit gates.
Up next: Topology and SWAP cost