Device topology and calibration heat maps
A quantum chip is a graph: qubits are the nodes, couplers are the edges, and only neighbours can run a two-qubit gate directly. Every chip is also calibrated several times a day, and the numbers decide which qubits are worth using. QubitLab draws both together as a heat map: the same picture IBM shows on its device pages, for every bundled fake backend and for your real machines.
How to read the map
- Node = qubit, labelled with its index. Node colour = readout error (how often a |0⟩ reads as 1 or a |1⟩ as 0): green is low, red is high, on a log scale between the best and worst qubit of that chip.
- Edge = coupler, drawn only where a two-qubit gate (CX, CZ or ECR) exists. Edge colour = that gate's error; a thick red edge is one the transpiler should avoid.
- Hover a node for T1, T2, readout and sx error; hover an edge for the two-qubit error. The tiles above the map give the queue, median T1/T2 and the best and worst coupler.
- Positions follow IBM's own device layouts (heavy-hex for Eagle and Heron, a line for 5-qubit chips, a grid for square lattices) so a map here looks like the one on quantum.cloud.ibm.com. Switch to the free layout to let the graph arrange itself.
What a heat map is
A heat map paints a number as a colour so that patterns jump out: a whole region of red couplers means a bad corner of the chip, a single red node means a qubit to route around. Errors span several orders of magnitude (a good readout is 0.5 %, a bad one 10 %), so the colour scale is logarithmic; otherwise everything but the worst element would look green. The scale is relative to the chip you are looking at, which is why the same error can be yellow on a good chip and green on a worse one.
| Number | Meaning | Typical (2026) | Why you care |
|---|---|---|---|
| T1 | Relaxation time: how long |1⟩ survives before decaying to |0⟩. | 100–400 µs | Circuits longer than a fraction of T1 lose their excitations. |
| T2 | Dephasing time: how long a superposition keeps its phase. | 50–300 µs | Interference (and every algorithm) needs phase; T2 ≤ 2·T1. |
| Readout error | Probability that the measured bit is wrong. | 0.5–5 % | Adds directly to the error of every histogram bar. |
| sx error | Error of the native single-qubit gate (√X). | 0.01–0.1 % | Usually negligible next to two-qubit gates. |
| CZ / ECR / CX error | Error of the native two-qubit gate on one coupler. | 0.1–2 % | The dominant cost; depth in two-qubit layers × this number ≈ your infidelity. |
Chip families, smallest to largest
Each map below is a bundled fake backend: a snapshot of a real IBM machine's calibration, so the colours are real measured numbers. The debugger, the simulator and Compare levels all use these same snapshots as their noise models.
Using the map when you run
- Compile at optimisation level 2 or 3: the transpiler reads the same calibration and prefers green qubits and green couplers (noise-aware layout).
- Count your two-qubit layers in Compare levels and multiply by the median coupler error for a quick fidelity estimate; the Debug tab with the same fake backend shows the exact drop gate by gate.
- For real hardware open the same panel from Run as → Hardware or the dashboard: calibration is refreshed by IBM a few times a day and cached here for ten minutes.